1. Field of the Present Invention
The present invention generally relates to the field of circuit design and more specifically to the field of programmable logic array circuit design.
2. History of Related Art
Programmable logic arrays (PLA's) are well known in the field of integrated circuits. A PLA typically includes an array of substantially identical cells where each cell includes one or more transistors and one or more interconnect elements. These cells may be placed as desired within a device. The individual cells can then be connected in a desired fashion using a customized contact layer, interconnect (metal) layer, or both to achieve a desired logical function. This type of design is particularly suitable for generating certain logic functions including a sum of products type of function. Using this technique enables manufacturers to produce customized logic with quick turnaround because wafers can be processed to the final interconnect layer. From there, the final product can be produced with only a small amount of incremental processing.
PLA's are also desirable for their high density and high performance. PLA's are typically either pseudo-static PLA's or dynamic PLA's. Both of these technologies employ a single (NMOS) transistor in the basic cell. Relative to alternative technologies such as full CMOS logic, PLA's are faster and require less area. PLA technology does, however, tend to exhibit higher power consumption.
In a well known technique, PLA cells are “tiled” such that the boundaries of one cell abut the boundaries of all adjacent cells. In this configuration, interconnection between adjacent cells can be achieved by incorporating an interconnect or wire segment in the cell that traverses the cell from one boundary to the opposing boundary. When cells having such wire segment(s) are tiled, the wire segments of adjacent cells form a continuous interconnect. These wire segments are typically used to provide a common input signal to a set of cells or to carry an output from the set of cells.
Interconnection using abutting wire segments as described simplifies the design process by eliminating the interconnect as a variable. All that is required is to select the appropriate type of cell for placement in the tiled array to achieve the desired function. Interconnection among the tiled cells is assured by the abutting wire segments. While the simplicity inherent in interconnection by abutment designs is desirable, it leaves no room to optimize the design by, for example, customizing wire segment lengths depending upon the logic function that is implemented. It would be desirable to optimize the length of wire segments in a PLA to minimize parasitic capacitance associated with the interconnects and thereby achieve improved performance through reduced signal delay and lower power consumption.